The Anatomy of an Instruction Pipeline Hazard

Software Development, OS & Low-Level Tech, AI & Machine Learning(hiraditya.github.io)view on HackerNews

Nvidia B200Instruction Pipeline HazardGPU ArchitectureCompiler SchedulingHardware ScoreboardVariable Latency OperationsLoad-Use Hazards

Author: somnial

Date: 7/14/2026

Article Summary:

The article discusses the anatomy of an instruction pipeline hazard in modern GPUs, specifically the Nvidia B200, and how it can lead to silent correctness bugs. The author presents a case study of a predicate-consumer under-stall hazard and proposes a method for mitigating it using on-silicon probing.